8155/6 Multifunction Device (memory+IO)
(Dated pre-2000)
- 2kbits static RAM 256x8
- 2 programmable 8 bit I/O ports
- 1 programmable 6 bit I/O port
- 1 programmable 14 bit binary counter/timer
- Internal address latch to demux AD0-AD7, using ALE line
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RESET | I | Reset input
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CE-bar or CE | I | Chip enable (55/56)
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ALE | I | Address latch enable
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RD-bar | I | Read input
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WR-bar | I | Write input
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IO/Mbar | I | I/O or memory section
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PA0-7 | I/O | Port A (8 bit)
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PB0-7 | I/O | Port B (8 bit)
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PC0-5 | I/O | Port C (6 bit)
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TIMER-IN | I | Timer input
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TIMER-OUT-bar | O | Timer output
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(ALE high, AD0=A0 etc)
0 | 0 | 0 | Command/status reg. |
0 | 0 | 1 | PA |
0 | 1 | 0 | PB |
0 | 1 | 1 | PC |
1 | 0 | 0 | Timer LSB |
1 | 0 | 1 | Timer MSB |
Timer command | IEB | IEA | PC | PB | PA |
- D0, D1: mode for PA and PB, 0=i/p, 1=o/p
- D2, D3: mode for PC
- D4, D5: interrupt enable for PA and PB, 0=disable 1=enable
- D6, D7: Timer command:
- 00: No effect
- 01: Stop if running else no effect
- 10: Stop after terminal count (TC) if running, else no effect
- 11: Start if not running, reload at TC if running.
Port C bits (D2, D3):
1 | 0 | 0 | I | I | I | I | I | I |
2 | 1 | 1 | O | O | O | O | O | O |
3 | 0 | 1 | O | O | O | STB-Abar | BF-A | INTR-A |
4 | 1 | 0 | STB-Bbar | BF-B | INtr-B | STB-Abar | BF-A | INTR-A |
I - input O - output
X | Timer | INTE-B | BF-B | INTR-B | INTE-A | BF-A | INTR-A |
D6: Timer. Latched high when TC is reached, low when status reg is read or reset is done.
MSB: |
M2 | M1 | T13 | T12 | T11 | T10 | T9 | T8 |
LSB: |
T7 | T6 | T5 | T4 | T3 | T2 | T1 | T0 |
M2, M1: mode bits:
- 00: Single square wave of wavelength TC/2 (TC/2,TC/2 if TC even; [TC+1/2],[TC-1/2] if TC odd)
- 01: Square waves of wavelength TC (TC/2,TC/2 if TC even; [TC+1/2],[TC-1/2] if TC odd)
- 10: Single pulse on the TC'th clock pulse
- 11: Single pulse on every TC'th clock pulse.