Comparison of digital logic families

(Important for Electronics DIC paper (MumbaiU B.E. sem5)

This table is based on one given in a textbook by R.P. Jain. I don't have the book and I don't remember anything else about it. Dated: 1999.

For detailed information, see: Buchanan, James E.: CMOS/TTL digital systems design / James E. Buchanan ; drawings by Bert D. Buchanan. New York : McGraw-Hill, 1990.

Family  Basic  Fanout    Pd       Noise   Prop. delay  Clock
         gate         (mW/gate)  immunity  (ns/gate)   (MHz)

TTL      NAND    10      10         VG         10        35
TTL-H    NAND    10      22         VG          6        50
TTL-L    NAND    20       1         VG         33         3
TTL-LS   NAND    20       2         VG          9.5      45
TTL-S    NAND    10      19         VG          3       125
TTL-AS   NAND    40      10         VG          1.5     175
TTL-ALS  NAND    20       1         VG          4        50

ECL 10K  OR-NOR  25      40-55       P          2       >60
ECL100K  OR-NOR  ??      40-55       P          0.75    600

MOS      NAND    20     0.2-10       G        300         2

74C    NOR/NAND  50    0.01/1       VG         70        10
74HC   NOR/NAND  20  0.0025/0.6     VG         18        60
74HCT  NOR/NAND  20  0.0025/0.6     VG         18        60
74AC   NOR/NAND  50   0.005/0.75    VG          5.25    100
74ACT  NOR/NAND  50   0.005/0.75    VG          4.75    100

• Figures of merit can be calculated as product of propagation delay and power dissipation Pd
• For CMOS, Pd is static/dynamic(1MHz) and figure of merit is calculated for each. TotalPd=staticPd + DynamicPd
• VG=VeryGood G=Good P=Poor