T states of 8085

Opcode fetch (OF):

T1
- External: IO/M=0, S0=1, S1=1. Address on AD0-AD7 (upto T1) and A8-A15 (upto T3). ALE is high.
- Internal: Reset-in sampled. HALT f/f sampled.
T2:
- External: AD0-AD7 disappears. RD is low. Memory device puts data on data bus AD0-7.
- Internal: PC incremented. Ready i/p is sampled at T2 rising edge (wait state added if low). HOLD sampled, HLDA f/f set if HOLD is high and OF is completed.
Wait state (optional):
- External: T2 levels of addr, data, and control lines maintained. No external ops.
- Internal: Samples Ready i/p at wait-state's rising edge. If low, adds another wait state.
T3:
- External: Data (opcode; this is OF) is transferred to instruction register. RD made high.
- Internal: Takes opcode from data bus into instruction register and gives to decoder.
T4:
- External: None
- Internal: Opcode decoded. Finds out whether to do T5 and T6, and number of bytes of instruction. During T4 of 4T, HLDA f/f is sampled (if set, T4 is completed, buses floated, HLDA high, HOLD state entered). During T4 of 6T, HOLD is sampled and HLDA f/f is set if necessary.
T5 and T6: Used only for CALL, CALL conditional, DCX, INX, PCHL, PUSH, SPHL, and RET conditional.
- External: None
- Internal: Performs condition check, stack/register operations. Samples HLDA f/f (if set, goes into hold mode after T6)

T1:
- IO/M=0, S0=0, S1=1.
- addr->addrbus (ALE high) (In memory read, addr is given by instruction. In operand fetch, addr is given by PC)
- HALT f/f sampled
- Other ops same as OF-1
T2:
- RD made low. AD0-AD7 removed.
- Other ops same as OF-2
Wait state: Same as OF-WS
T3:
- data: memory->8085->internal data bus
- RD high
- If fetching operand, PC is incremented
- Same as OF-3 except data is not put in instruction register, and HLDA f/f is sampled.

(Dated pre-2000)