8259 Programmable Interrupt Controller
- 8 levels of interrupts.
- Can be cascaded in master-slave configuration to handle 64 levels of interrupts.
- Internal priority resolver.
- Fixed priority mode and rotating priority mode.
- Individually maskable interrupts.
- Modes and masks can be changed dynamically.
- Accepts IRQ, determines priority, checks whether incoming priority > current level being serviced, issues interrupt signal.
- In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8 bit vector number.
- Polled and vectored mode.
- Starting address of ISR or vector number is programmable.
- No clock required.
|
D0-D7 | Bi-directional, tristated, buffered data lines. Connected to data bus directly or through buffers |
RD-bar | Active low read control |
WR-bar | Active low write control |
A0 | Address input line, used to select control register |
CS-bar | Active low chip select |
CAS0-2 | Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on these lines. In slave mode, the PIC reads slave ID no. from master on these lines. It may be regarded as slave-select. |
SP-bar / EN-bar | Slave program / enable. In non-buffered mode, it is SP-bar input, used to distinguish master/slave PIC. In buffered mode, it is output line used to enable buffers |
INT | Interrupt line, connected to INTR of microprocessor |
INTA-bar | Interrupt ack, received active low from microprocessor |
IR0-7 | Asynchronous IRQ input lines, generated by peripherals. |
|
D0: IC4: 0=no ICW4, 1=ICW4 required
D1: SNGL: 1=Single PIC, 0=Cascaded PIC
D2: ADI: Address interval. Used only in 8085, not 8086. 1=ISR's are 4 bytes apart (0200, 0204, etc) 0=ISR's are 8 byte apart (0200, 0208, etc)
D3: LTIM: level triggered interrupt mode: 1=All IR lines level triggered. 0=edge triggered
D4-D7: A5-A7: 8085 only. ISR address lower byte segment. The lower
byte is
of which A7, A6, A5 are provided by D7-D5 of ICW1 (if ADI=1), or A7, A6 are provided if ADI=0. A4-A0 (or A5-A0) are set by 8259 itself:
ADI=1 (spacing 4 bytes)
IR0 | A7 | A6 | A5 | 0 | 0 | 0 | 0 | 0 |
IR1 | A7 | A6 | A5 | 0 | 0 | 1 | 0 | 0 |
IR2 | A7 | A6 | A5 | 0 | 1 | 0 | 0 | 0 |
IR3 | A7 | A6 | A5 | 0 | 1 | 1 | 0 | 0 |
IR4 | A7 | A6 | A5 | 1 | 0 | 0 | 0 | 0 |
IR5 | A7 | A6 | A5 | 1 | 0 | 1 | 0 | 0 |
IR6 | A7 | A6 | A5 | 1 | 1 | 1 | 0 | 0 |
IR7 | A7 | A6 | A5 | 1 | 1 | 1 | 0 | 0 |
|
ADI=0 (spacing 8 bytes)
IR0 | A7 | A6 | 0 | 0 | 0 | 0 | 0 | 0 |
IR1 | A7 | A6 | 0 | 0 | 1 | 0 | 0 | 0 |
IR2 | A7 | A6 | 0 | 1 | 0 | 0 | 0 | 0 |
IR3 | A7 | A6 | 0 | 1 | 1 | 0 | 0 | 0 |
IR4 | A7 | A6 | 1 | 0 | 0 | 0 | 0 | 0 |
IR5 | A7 | A6 | 1 | 0 | 1 | 0 | 0 | 0 |
IR6 | A7 | A6 | 1 | 1 | 0 | 0 | 0 | 0 |
IR7 | A7 | A6 | 1 | 1 | 1 | 0 | 0 | 0 |
|
Higher byte of ISR address (8085), or 8 bit vector address (8086).
|
Master | S7 | S6 | S5 | S4 | S3 | S2 | S1 | S0 |
Slave | 0 | 0 | 0 | 0 | 0 | ID3 | ID2 | ID1 |
|
- Master mode: 1 indicates slave is present on that interrupt, 0 indicates direct interrupt
- Slave mode: ID3-ID2-ID1 is the slave ID number. Slave 4 on IR4 has ICW3=04h (0000 0100)
- SFNM: 1=Special Fully Nested Mode, 0=FNM
- M/S: 1=Master, 0=Slave
- AEOI: 1=Auto End of Interrupt, 0=Normal
- Mode: 0=8085, 1=8086
IRn is masked by setting Mn to 1; mask cleared by setting Mn to 0 (n=0..7)
EOI | 0 | 0 | 1 | Non specific EOI (L3L2L1=000) |
0 | 1 | 1 | Specific EOI command (Interrupt to clear given by L3L2L1) |
Auto rotation of priorities (L3L2L1=000) | 1 | 0 | 1 | Rotate priorities on non-specific EOI |
1 | 0 | 0 | Rotate priorities in auto EOI mode set |
0 | 0 | 0 | Rotate priorities in auto EOI mode clear |
Specific rotation of priorities (Lowest priority ISR=L3L2L1) | 1 | 1 | 1 | Rotate priority on specific EOI command (resets current ISR bit) |
1 | 1 | 0 | Set priority (does not reset current ISR bit) |
0 | 1 | 0 | No operation |
ESMM | SMM | Effect |
0 | X | No effect |
1 | 0 | Reset special mask |
1 | 1 | Set special mask |
- One or more of the IR lines goes high.
- Corresponding IRR bit is set.
- 8259 evaluates the request and sends INT to CPU.
- CPU sends INTA-bar.
- Highest priority ISR is set. IRR is reset.
- 8259 releases CALL instruction on data bus.
- CALL causes CPU to initiate two more INTA-bar's.
- 8259 releases the subroutine address, first lowbyte then highbyte.
- ISR bit is reset depending on mode.