8259 Programmable Interrupt Controller


Features:


Pinout

[8259 pinout]
D0-D7Bi-directional, tristated, buffered data lines. Connected to data bus directly or through buffers
RD-barActive low read control
WR-barActive low write control
A0Address input line, used to select control register
CS-barActive low chip select
CAS0-2Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on these lines. In slave mode, the PIC reads slave ID no. from master on these lines. It may be regarded as slave-select.
SP-bar / EN-barSlave program / enable. In non-buffered mode, it is SP-bar input, used to distinguish master/slave PIC. In buffered mode, it is output line used to enable buffers
INTInterrupt line, connected to INTR of microprocessor
INTA-barInterrupt ack, received active low from microprocessor
IR0-7Asynchronous IRQ input lines, generated by peripherals.

Block diagram

[8259 block diagram]

ICW1 (Initialisation Command Word One)

A0
0
D7D6D5D4D3D2D1D0
A7A6A51LTIMADISNGLIC4
D0: IC4: 0=no ICW4, 1=ICW4 required
D1: SNGL: 1=Single PIC, 0=Cascaded PIC
D2: ADI: Address interval. Used only in 8085, not 8086. 1=ISR's are 4 bytes apart (0200, 0204, etc) 0=ISR's are 8 byte apart (0200, 0208, etc)
D3: LTIM: level triggered interrupt mode: 1=All IR lines level triggered. 0=edge triggered
D4-D7: A5-A7: 8085 only. ISR address lower byte segment. The lower byte is
A7A6A5A4A3A2A1A0
of which A7, A6, A5 are provided by D7-D5 of ICW1 (if ADI=1), or A7, A6 are provided if ADI=0. A4-A0 (or A5-A0) are set by 8259 itself:

ADI=1 (spacing 4 bytes)
IRQA7A6A5A4A3A2A1A0
IR0A7A6A500000
IR1A7A6A500100
IR2A7A6A501000
IR3A7A6A501100
IR4A7A6A510000
IR5A7A6A510100
IR6A7A6A511100
IR7A7A6A511100
ADI=0 (spacing 8 bytes)
IRQA7A6A5A4A3A2A1A0
IR0A7A6000000
IR1A7A6001000
IR2A7A6010000
IR3A7A6011000
IR4A7A6100000
IR5A7A6101000
IR6A7A6110000
IR7A7A6111000

ICW2 (Initialisation Command Word Two)

Higher byte of ISR address (8085), or 8 bit vector address (8086).

A0
1
D7D6D5D4D3D2D1D0
A15A14A13A12A11A10A9A8

ICW3 (Initialisation Command Word Three)

A0
1
 D7D6D5D4D3D2D1D0
MasterS7S6S5S4S3S2S1S0
Slave00000ID3ID2ID1

ICW4 (Initialisation Command Word Four)

A0
1
D7D6D5D4D3D2D1D0
000SFNMBUFM/SAEOIMode

OCW1 (Operational Command Word One)

A0
1
D7D6D5D4D3D2D1D0
M7M6M5M4M3M2M1M0

IRn is masked by setting Mn to 1; mask cleared by setting Mn to 0 (n=0..7)


OCW2 (Operational Command Word Two)

A0
1
D7D6D5D4D3D2D1D0
RSLEOI00L3L2L1

RSLEOIAction
EOI001Non specific EOI (L3L2L1=000)
011Specific EOI command (Interrupt to clear given by L3L2L1)
Auto rotation of priorities (L3L2L1=000)101Rotate priorities on non-specific EOI
100Rotate priorities in auto EOI mode set
000Rotate priorities in auto EOI mode clear
Specific rotation of priorities (Lowest priority ISR=L3L2L1)111Rotate priority on specific EOI command (resets current ISR bit)
110Set priority (does not reset current ISR bit)
010No operation

OCW3 (Operational Command Word Three)

A0
1
D7D6D5D4D3D2D1D0
D7ESMMSMM01MODERIRRIS

ESMMSMMEffect
0XNo effect
10Reset special mask
11Set special mask

Interrupt sequence (single PIC)

  1. One or more of the IR lines goes high.
  2. Corresponding IRR bit is set.
  3. 8259 evaluates the request and sends INT to CPU.
  4. CPU sends INTA-bar.
  5. Highest priority ISR is set. IRR is reset.
  6. 8259 releases CALL instruction on data bus.
  7. CALL causes CPU to initiate two more INTA-bar's.
  8. 8259 releases the subroutine address, first lowbyte then highbyte.
  9. ISR bit is reset depending on mode.

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